1. Field of the Invention
The present invention relates to a multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure, and more particularly, to technology capable of minimizing power consumption and reducing a chip size by enabling sharing of an amplifier used in a multi-bit pipeline ADC.
2. Discussion of Related Art
In order to process an image signal in an image system, a small analog signal needs to be converted into a digital signal sensitive to a noise. The conversion of the analog signal into the digital signal is performed using an ADC.
Since image data output from a sensor is very minute, the imaging system requires a high-resolution ADC capable of distinguishing a small signal. In addition to the imaging system, communication systems and image processing/application systems, such as mobile communication devices, asynchronous digital subscriber loops (ADSLs), IMT-2000, digital camcorders, and high-definition televisions (HDTVs), also require high-resolution ADCs that have a high resolution (12-/14 bit) and a high sampling rate of several tens of MHz.
Among the variety of known ADC structures, a flash ADC, a folding ADC, a subranging ADC, and a pipeline ADC are able to process signals at a high-speed. Recently, a pipeline ADC structure, which consumes low power and occupies a small area, has been widely used to satisfy both conditions of high-speed signal processing and a high resolution at the same time.
A conventional pipeline ADC may be classified into a single-bit structure, which decides 1 bit for each stage, or a multi-bit structure, which decides 2 bits or more for each stage. In general, a high-resolution pipeline ADC has adopted the multi-bit structure to a greater extent than the single-bit structure which requires many stages, because the multi-bit structure decides many bits at each (a first) stage to lessen the influence of the next stage and optimize power consumption and an occupied area.
FIG. 1 is a circuit diagram of a conventional multi-bit pipeline ADC.
Referring to FIG. 1, the multi-bit pipeline ADC includes several stages, so that an analog input signal Vin passes through a sample-and-hold amplifier (SHA) 10 and is converted into a digital signal at each of stages ST1 to STk, and is output. For example, the stage ST1 includes an N-bit flash ADC 20 and an N-bit multiplying digital-to-analog converter (MDAC) 30. The N-bit flash ADC 20 receives an analog signal from a preceding stage, converts the analog signal into a digital signal, and outputs the digital signal. The N-bit MDAC 30 converts a difference between the digital signal output from the N-bit flash ADC 20 and the preceding-stage output signal into an analog signal and outputs the amplified analog signal to the next stage.
When analog-to-digital conversion is to produce 4 bits at each stage, the following operation is performed at each stage: a 4-bit flash ADC 20 receives an input analog signal and outputs a 4-bit digital signal, and a 4-bit MDAC 30 converts a difference between the digital signal output from the 4-bit flash ADC 20 and the preceding-stage output signal into an analog signal and outputs the amplified analog signal to the next stage.
In other words, the multi-bit pipeline ADC constituted as shown in FIG. 1 converts a part of an analog signal into a digital signal at each stage, so that the signal conversion is achieved as intended.
In the multi-bit pipeline ADC constituted as shown in FIG. 1, the SHA 10 used at an input terminal to remove a sampling error of input voltages between the MDAC and the flash ADC of the first stage comprises one amplifier and a plurality of capacitors. Also, this circuit needs a wide bandwidth as well as a large phase margin of about 70˜80 degrees to achieve high speed and high linearity. Therefore, as the operation speed of the ADC increases, a large amount of power is consumed by the amplifier of the SHA 10.
Various amplifier sharing method are suggested to reduce such power consumption. For example, an amplifier can be shared between adjacent pipeline stages operating opposite clock phase. However, this scheme is not adaptable to a front-end SHA and following first-stage MDAC which take up a major portion of the overall ADC power, because the SHA and MDAC have large differences in their operating conditions, especially, in multi-bit-per stage pipelined ADCs. Thus, most methods reduce power consumption by sharing an amplifier between only MDAC 30 blocks having the same structure and feedback factor as shown in E of FIG. 1.
More specifically, the SHA 10 outputs an input signal using the same value and thus has a feedback factor of about 1, and the MDAC 30 amplifies an input signal by a factor of 4 or more and thus has a feedback factor of a quarter or less. Due to such a difference in feedback factor, it is not possible to simultaneously satisfy bandwidths and phase margins required by each block when the same amplifier is shared. What's more, sharing the same amplifier between the SHA 10 and the MDAC 30 increases power consumption and chip size. For these reasons, it is difficult to share an amplifier between the SHA 10 and the MDAC 30. Thus, an amplifier is only shared between the MDAC 30 blocks.
Thus, in order to reduce the power consumption and chip size of a multi-bit pipeline ADC, there is need of a way to share an amplifier between an SHA and an MDAC while satisfying requirements on the operation characteristics of each block.